1. Field of the Invention
This invention pertains in general to portable electronic devices and in particular to reducing power consumption of such devices by controlling the clock frequencies in the devices.
2. Background of the Invention
The need for portable electronic devices, also referred to as xe2x80x9celectronic appliancesxe2x80x9d is growing rapidly. Numerous small devices, such as the PALM PILOT organizer from 3COM, INC. and MICROSOFT WINDOWS CE-based palm computers have become ubiquitous in society. As the sizes of the devices decrease and the processing powers increase, these devices will become even more prevalent. For example, solid-state music players, smart phones, screen phones, digital cameras, and other Internet-ready electronic appliances will soon become mainstream.
By nature, a portable electronic device should be as small and light as possible. Accordingly, there is a desire to reduce the amount of circuitry within the device by combining functions previously performed by separate integrated circuits (ICs) into a single complementary metal oxide semiconductor (CMOS) application specific integrated circuit (ASIC). For example, a single ASIC for a portable electronic device may include a central processing unit (CPU), a digital signal processor (DSP), a peripheral controller, a memory controller, a video controller, a clock controller, and an interrupt controller.
However, the CMOS ASIC requires a significant amount of power to provide this functionality. Since the battery is often one of the heaviest and bulkiest components of a portable electronic device, there is a strong desire to minimize power consumption by the ASIC and other components. Although a single ASIC typically uses less power than do separate ICs, there is a desire to reduce the power use even further.
For example, in a CMOS ASIC, the majority of power dissipation is due to the alternating current (AC) element that results from the charging and discharging of the capacitance in the chip. The power dissipation of a typical logic gate in a CMOS ASIC is approximated by the following equation:
Power Dissipation=Vdd2* C * Freq;
where Vdd is the voltage supply to a logic gate, C is the total intrinsic and extrinsic capacitance loading of the logic gate, and Freq is the toggle frequency of the logic gate. The total power dissipation of the CMOS ASIC is the sum of all power dissipated at each logic gate at the gate""s respective toggle frequency and total capacitance loading.
Thus, the major power draws on the ASIC are the clocks generated by the clock controller and the digital logic that is controlled directly or indirectly by the clocks. A typical clock controller, for example, may generate separate clocks for driving the CPU, system bus, memory, and peripherals. The operating speed of the driven device is dependent on the frequency of its clock. Since there is a general desire to operate the device at its highest speed, the clocks are usually run at a high frequency and therefore dissipate power at a high rate.
Moreover, if a device is operated with a clock frequency higher than is necessary, the power utilized to operate at the higher-frequency clock is essentially wasted. For example, the system memory may run on a 100 MHz clock. However, an external peripheral accessing the memory, such as an infra-red (IR) transceiver, may support data transfers at only a fraction of the speed of which the memory is capable. Assuming that there are no concurrent memory requests from other devices, the power needed to drive the system memory at a higher frequency than is needed to support the IR transceiver is essentially wasted.
Some ASICs contain special circuitry to reduce power consumption by disabling external memory devices using the xe2x80x9cCKExe2x80x9d signal when there are no memory accesses. While the external memory devices save power by entering a low power state when disabled, the memory clock generated by the clock controller remains running at full speed. In addition, the xe2x80x9cClock I/Oxe2x80x9d pin to the external memory also toggles continuously, thereby consuming power on the clock driver I/O pad and the clock receiver I/O pads.
Accordingly, there is a need for a low-power CMOS ASIC for a portable electronic device. Preferably, the ASIC would minimize power wasted by free running clocks and mismatches between the bandwidth requirements of different devices. The ASIC should also achieve these goals without sacrificing system performance.
The above problems are resolved by an application specific integrated circuit (ASIC) for a portable electronic device that has a clock controller that dynamically and automatically varies the frequency of on-chip clocks in response to bandwidth requirements of the driven logic. The ASIC preferably includes a central processing unit (CPU), a digital signal processor, and a small amount of static random access memory (SRAM). In addition, the ASIC includes system and memory busses coupling together the CPU, a memory controller for accessing external memory devices, controllers for supporting color and/or monochrome display devices, an interrupt controller, and a direct memory access (DMA) controller for providing other devices access to the memory controller without requiring CPU intervention. The ASIC also preferably includes a peripheral bus coupling other peripherals to the system bus. Devices on the peripheral bus include universal asynchronous receiver/transmitters (UARTs), MMC card interfaces, and synchronous serial interfaces. The peripheral bus is also directly connected to the DMA controller.
The ASIC also includes one or more oscillators used by phase locked loops (PLLs) to generate one or more master clocks. These master clocks are received by a system clock controller which derives various clocks of different frequencies from the master clocks. These derived clocks are used to drive the various controllers and peripherals described above. For example, the system clock controller preferably generates a memory clock for clocking the memory controller and the external memory devices, a bus clock for clocking the system bus, a CPU clock for clocking the CPU, and one or more peripheral clocks for clocking the various peripheral controllers and peripherals coupled to the ASIC.
The various devices in the ASIC that can be accessed by other devices in the ASIC, such as the system bus, the memory controller, and the SRAM, are referred to as xe2x80x9cresources.xe2x80x9d The speed at which a resource is clocked affects the rate at which the resource can process data (i.e., the bandwidth of the resource). The devices in the ASIC that can access a resource are referred to as xe2x80x9ccontrollers.xe2x80x9d For example, a UART controller is a controller because it can access the memory controller via the DMA controller. Typically, a controller will access a resource within a given bandwidth range.
Preferably, every controller has a request line coupled to the system clock controller to indicate when the controller is accessing a resource. The controller may have a single request line to indicate that it is accessing any resource, or the controller may have a request line for each resource in the ASIC that the controller can access. In addition, the system clock controller has a programmable bandwidth register associated with each controller for holding a value representing the bandwidth utilized by the controller. The system clock controller also preferably includes an adder, a frequency table, and a multiplexer (MUX) for each clocked resource.
When a controller accesses a resource, the controller signals the system clock controller via the request line. The system clock controller, in turn, uses the adder to sum the values held in the bandwidth registers of all of the controllers that are currently accessing the resource. The resulting sum is then used an index to an entry in the frequency table. The contents of the entry are applied to the selection lines of the MUX and dynamically select the appropriate clock frequency for the resource.
Thus, the clock frequency for the resource is automatically determined by the total bandwidth utilization of the controllers requesting access to the resource. Accordingly, the clock frequency is preferably chosen so that the bandwidth of the resource closely matches the needed bandwidth. As a result, little power is wasted due to operating the resource at a higher clock frequency than is necessary. A preferred embodiment of the present invention further conserves power by shutting off the memory clock when no controllers are requesting access to the memory controller.